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HY5PS121621CFP-S6I 数据表(PDF) 15 Page - Hynix Semiconductor

部件名 HY5PS121621CFP-S6I
功能描述  512Mb DDR2 SDRAM
Download  38 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5PS121621CFP-S6I 数据表(HTML) 15 Page - Hynix Semiconductor

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Rev. 0.8 / Oct. 2007
15
1HY5PS12421C(L)FP-xI
1HY5PS12821C(L)FP-xI
1HY5PS121621C(L)FP-xI
3.3.3 OCD default characteristics
Description
Parameter
Min
Nom
Max
Unit
Notes
Output impedance
See full strength default
driver characteristics
ohms
1
Output impedance step size for OCD calibration
0
1.5
ohms
6
Pull-up and pull-down mismatch
0
4
ohms
1,2,3
Output slew rate
Sout
1.5
-
5
V/ns
1,4,5,6,7,8
Note
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for
timing,voltage, and
slew rate are no longer applicable if OCD is changed from default settings. Please refer to the Device Operation &
Timing Diagram
of DDR2 for the Full Strength Default Driver Characteristics.
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh
must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement
condition for output sink
dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V
and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/
variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
VTT
25 ohms
Output
(Vout)
Reference
point


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