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HY5S5B2BLF-SE 数据表(PDF) 38 Page - Hynix Semiconductor |
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HY5S5B2BLF-SE 数据表(HTML) 38 Page - Hynix Semiconductor |
38 / 54 page Rev 1.0 / Apr. 2006 38 11 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series WRITE to READ The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency. The preceding write operation (WRIT) writes only the data input before the read command. The data bus must go into a high-impedance state at least one cycle before output of the latest data. Note: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preced- ing write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is nec- essary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). CLK Don't Care DQ WRITE READ Command BA, Col b Address DQ DI b0 DI b1 DO n0 DO n2 DOn3 BL = 4 DO n1 DI b0 DI b1 BL = 4 CL = 3 BA, Col n CL = 2 DO n0 DO n2 DOn3 DO n1 |
类似零件编号 - HY5S5B2BLF-SE |
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类似说明 - HY5S5B2BLF-SE |
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