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HY5S5B2BLF-HE 数据表(PDF) 13 Page - Hynix Semiconductor

部件名 HY5S5B2BLF-HE
功能描述  256M (8Mx32bit) Mobile SDRAM
Download  54 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5S5B2BLF-HE 数据表(HTML) 13 Page - Hynix Semiconductor

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Rev 1.0 / Apr. 2006
13
11
256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2BLF(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Parameter
Symbol
6
H
S
Unit Note
Min
Max
Min
Max
Min
Max
System Clock
Cycle Time
CAS Latency=3
tCK3
6.0
1000
7.5
1000
9.5
1000
ns
Clock High Pulse Width
tCHW
2.0
-
2.5
-
3.0
-
ns
1
Clock Low Pulse Width
tCLW
2.0
-
2.5
-
3.0
-
ns
1
Access Time From Clock CAS Latency=3
tAC3
-5.4
-6.5
-7.0
ns
2
Data-out Hold Time
tOH
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
tDS
2.0
-
2.0
-
2.0
-
ns
1
Data-Input Hold Time
tDH
1.0
-
1.0
-
1.0
-
ns
1
Address Setup Time
tAS
2.0
-
2.0
-
2.0
-
ns
1
Address Hold Time
tAH
1.0
-
1.0
-
1.0
-
ns
1
CKE Setup Time
tCKS
2.0
-
2.0
-
2.0
-
ns
1
CKE Hold Time
tCKH
1.0
-
1.0
-
1.0
-
ns
1
Command Setup Time
tCS
2.0
-
2.0
-
2.0
-
ns
1
Command Hold Time
tCH
1.0
-
1.0
-
1.0
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1.0
-
1.0
-
1.0
-
ns
CLK to Data Output in
High-Z Time
CAS Latency=3
tOHZ3
5.4
6.5
7.0
ns


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