Rev. 1.2 /June. 2008
8
HY5FS123235AFCP
REGISTER DEFINITION
MODE REGISTER (MR)
The Mode Register is used to define the specific mode of operation of the GDDR4 SDRAM. This includes the definition
of Write Latency, Write Recovery, DLL Reset, Test Mode and CAS latency as shown in Figure 3.
The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0=0, BA1=0 and BA2=0)
and will retain the stored information until it is reprogrammed or the device loses power (except bit A8, which is self-
clearing).
Reprogramming the mode register will not alter the contents of the memory. The Mode Register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating
any subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are reserved for
future use and must be programmed to 0.
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