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HY5FS123235AFCP-07 数据表(PDF) 29 Page - Hynix Semiconductor

部件名 HY5FS123235AFCP-07
功能描述  512M (16Mx32) GDDR4 SDRAM
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

HY5FS123235AFCP-07 数据表(HTML) 29 Page - Hynix Semiconductor

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Rev. 1.2 /June. 2008
29
HY5FS123235AFCP
SELF REFRESH
The SELF REFRESH command (see Figure 21) can be used to retain data in the GDDR4 SDRAM, even if the rest of the
system is powered down. When in the self refresh mode, the GDDR4 SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE# is disabled(HIGH). The DLL
is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF
REFRESH. The on-die termination is also disabled upon entering Self Refresh except for CKE# and enabled upon
exiting Self Refresh. (tXSRD must occur before a read command can be issued, tXSNR must occur before a non-read
command can be issued.) Input signals except CKE# are Dont Care during SELF REFRESH.
The procedure for exiting self refresh (see Figure 22) requires a sequence of commands. First, CK and CK# must be
stable prior to CKE# going back LOW. Once CKE# is LOW, the GDDR4 SDRAM must have NOP commands issued for
tXSNR because time is required for the completion of any internal refresh in progress.
A simple algorithm for meeting both refresh and DLL requirements and output calibration is to apply NOPs for tXSRD
cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate.
If the GDDR4 device enters SELF REFRESH with the DLL disabled the GDDR4 device will exit SELF REFRESH with the
DLL disabled.
CK #
CK
CKE # L O W
CS #
RAS #
CAS #
WE #
A9 -A 1 2
A0 ,A 2 ,A3 ,A 7
A8
BA 0-BA 2
A1,A 5 ,A6
Au to -R e fre s h
CK #
CK
CKE # H IG H
CS #
RA S #
CAS#
WE #
A9 -A 1 2
A0 ,A 2 ,A3 ,A 7
A8
BA 0-B A 2
A1 ,A 5 ,A6
Se lf-R e fre s h
Figure 20: AUTO REFRESH command Figure 21: SELF REFRESH command


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