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H57V2562GTR-50J 数据表(PDF) 11 Page - Hynix Semiconductor |
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H57V2562GTR-50J 数据表(HTML) 11 Page - Hynix Semiconductor |
11 / 23 page Rev 1.0 / Aug. 2009 11 111 Synchronous DRAM Memory 256Mbit H57V2562GTR-xxI Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Parameter Speed (MHz) 200 166 133 Unit Note Min Max Min Max Min Max System Clock Cycle Time CL = 3 tCK3 5.0 1000 6.0 1000 7.5 1000 ns CL = 2 tCK2 - - 1000 10 1000 ns Clock High Pulse Width tCHW 2.0 - 2.5 - 2.5 - ns 1 Clock Low Pulse Width tCLW 2.0 - 2.5 - 2.5 - ns 1 Access Time From Clock CL = 3 tAC3 - 4.5 - 5.4 - 5.4 ns 2 CL = 2 tAC2 -- --- 6 ns 2 Data-out Hold Time tOH 2.0 - 2.0 - 2.5 - ns Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - ns 1 Address Setup Time tAS 1.5 - 1.5 - 1.5 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.0 - ns CLK to Data Output in High-Z Time CL = 3 tOHZ3 - 4.5 2.7 5.4 2.7 5.4 ns CL = 2 tOHZ2 -- -- 3 6 ns |
类似零件编号 - H57V2562GTR-50J |
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类似说明 - H57V2562GTR-50J |
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