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H57V2562GTR-60L 数据表(PDF) 12 Page - Hynix Semiconductor |
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H57V2562GTR-60L 数据表(HTML) 12 Page - Hynix Semiconductor |
12 / 23 page Rev 1.0 / Aug. 2009 12 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Note: 1. A new command can be given tRC after self refresh exit. Parameter Speed (MHz) 200 166 133 Unit Note Min Max Min Max Min Max RAS Cycle Time Operation tRC 55 - 60 - 63 - ns Auto Refresh tRRC 55 - 60 - 63 - ns RAS to CAS Delay tRCD 15 - 18 - 20 - ns RAS Active Time tRAS 38.7 100K 42 100K 42 100K ns RAS Precharge Time tRP 15 - 18 - 20 - ns RAS to RAS Bank Active Delay tRRD 10 - 12 - 15 - ns CAS to CAS Delay tCCD 1 - 1-1- CLK Write Command to Data-In Delay tWTL 0- 0 -0 - CLK Data-in to Precharge Command tDPL 2 - 2-2- CLK Data-In to Active Command tDAL tDPL + tRP DQM to Data-Out Hi-Z tDQZ 2 - 2-2- CLK DQM to Data-In Mask tDQM 0 - 0-0- CLK MRS to New Command tMRD 2 - 2-2- CLK Precharge to Data Output High-Z CL = 3 tPROZ3 3 - 3-3- CLK CL = 2 tPROZ2 -- -- 2 - CLK Power Down Exit Time tDPE 1 - 1-1- CLK Self Refresh Exit Time tSRE 1 - 1-1- CLK 1 Refresh Time tREF -64- 64 -64 ms |
类似零件编号 - H57V2562GTR-60L |
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类似说明 - H57V2562GTR-60L |
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