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H57V2562GFR-75C 数据表(PDF) 6 Page - Hynix Semiconductor

部件名 H57V2562GFR-75C
功能描述  256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
Download  23 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H57V2562GFR-75C 数据表(HTML) 6 Page - Hynix Semiconductor

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Rev 1.0 / Aug. 2009
6
111
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
54_TSOPII Pin DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
CLK
INPUT
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
CKE
INPUT
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
CS
INPUT
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
INPUT
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A12
INPUT
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS, WE
INPUT
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM
I/O
Data Mask:
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
I/O
Data Input / Output:
Multiplexed data input / output pin
VDD / VSS
SUPPLY
Power supply for internal circuits and input buffers
VDDQ / VSSQ
SUPPLY
Power supply for output buffers
NC
-
No connection : These pads should be left unconnected


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