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H57V2562GFR-75C 数据表(PDF) 22 Page - Hynix Semiconductor

部件名 H57V2562GFR-75C
功能描述  256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H57V2562GFR-75C 数据表(HTML) 22 Page - Hynix Semiconductor

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Rev 1.0 / Aug. 2009
22
111
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Current
State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS CAS
WE
BA0,
BA1
ADDR
Any State
other than
listed above
H
H
XX
XX
X
X
Refer to operations of
the Current State
Truth Table
H
L
XX
XX
X
X
Begin Clock Suspend
next cycle
L
H
XX
XX
X
X
Exit Clock Suspend
next cycle
L
L
XX
XX
X
X
Maintain Clock Suspend


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