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H57V2562GFR-75C 数据表(PDF) 18 Page - Hynix Semiconductor

部件名 H57V2562GFR-75C
功能描述  256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H57V2562GFR-75C 数据表(HTML) 18 Page - Hynix Semiconductor

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Rev 1.0 / Aug. 2009
18
111
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
CURRENT STATE TRUTH TABLE (Sheet 3 of 4)
Current
State
Command
Action
Notes
CS RAS CAS WE
BA0/
BA1
A
max-A0
Description
Precharging
L
L
L
L
OP CODE
Mode Register Set
ILLEGAL
13
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
LL
H
L
BA
X
Precharge
No Operation:
Bank(s) idle after tRP
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
LH
H
H
X
X
No Operation
No Operation:
Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation:
Bank(s) idle after tRP
Row
Activating
L
L
L
L
OP CODE
Mode Register Set
ILLEGAL
13
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,11,1
2
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
LH
H
H
X
X
No Operation
No Operation: Row
Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation: Row
Active after tRCD
Write
Recovering
L
L
L
L
OP CODE
Mode Register Set
ILLEGAL
13
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
Start Write:
Optional AP(A10=H)
L
H
L
H
BA
Col Add. A10
Read/ReadAP
Start Read: Optional
AP(A10=H)
9
LH
H
H
X
X
No Operation
No Operation:
Row Active after tDPL


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