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H57V2562GFR-75C 数据表(PDF) 10 Page - Hynix Semiconductor

部件名 H57V2562GFR-75C
功能描述  256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
Download  23 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H57V2562GFR-75C 数据表(HTML) 10 Page - Hynix Semiconductor

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Rev 1.0 / Aug. 2009
10
111
Synchronous DRAM Memory 256Mbit
H57V2562GFR Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Note:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. H57V2562GFR-XXC Series: Normal,
H57V2562GFR-XXL Series: Low Power
Parameter
Symbol
Test Condition
Speed
(MHz)
Unit
Note
166
133
Operating
Current
IDD1
Burst length=1, One bank active
tRC
≥ tRC(min), IOL=0mA
90
70
mA
1
Precharge
Standby
Current
in Power Down
Mode
IDD2P
CKE
≤ VIL(max), tCK = 15ns
2
mA
IDD2PS
CKE
≤ VIL(max), tCK = ∞
2mA
Precharge
Standby
Current
in Non Power
Down Mode
IDD2N
CKE
≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
≥ VDD-0.2V or ≤ 0.2V
15
mA
IDD2NS
CKE
≥ VIH(min), tCK = ∞
Input signals are stable.
8
Active Standby
Current in
Power Down
Mode
IDD3P
CKE
≤ VIL(max), tCK = 15ns
5
mA
IDD3PS
CKE
≤ VIL(max), tCK = ∞
5
Active Standby
Current in Non
Power Down
Mode
IDD3N
CKE
≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins
≥ VDD-0.2V or ≤ 0.2V
28
mA
IDD3NS
CKE
≥ VIH(min), tCK = ∞
Input signals are stable.
20
Burst Mode Op-
erating Current
IDD4
tCK
≥ tCK(min), IOL=0mA
All banks active
100
80
mA
1
Auto Refresh
Current
IDD5
tRC
≥ tRC(min), All banks active
160
140
mA
2
Self Refresh
Current
IDD6
CKE
≤ 0.2V
Normal
2
mA
3
Low Power
1


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