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H55S1G32MFP-A3 数据表(PDF) 24 Page - Hynix Semiconductor

部件名 H55S1G32MFP-A3
功能描述  1Gb (32Mx32bit) Mobile SDRAM
Download  53 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H55S1G32MFP-A3 数据表(HTML) 24 Page - Hynix Semiconductor

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Rev 1.2 / Jun. 2008
24
11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Notes :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Current
State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS CAS
WE
BA0,
BA1
A
max-
A0
All
Banks
Idle
HH
H
X
X
X
Refer to the idle State section
of the Current State
Truth Table
3
HH
L
H
X
X
3
HH
L
L
H
X
3
HH
L
L
L
H
X
X
Auto Refresh
H
H
L
L
L
L
OP CODE
Mode Register Set
4
HL
H
X
X
X
Refer to the idle State section
of the Current State
Truth Table
3
HL
L
H
X
X
3
HL
L
L
H
X
3
HL
L
L
L
H
X
X
Entry Self Refresh
4
H
L
L
L
L
L
OP CODE
Mode Register Set
L
X
XX
XX
X
X
Power Down
4
Any State
other than
listed above
H
H
XX
XX
X
X
Refer to operations of
the Current State
Truth Table
H
L
XX
XX
X
X
Begin Clock Suspend
next cycle
L
H
XX
XX
X
X
Exit Clock Suspend
next cycle
L
L
XX
XX
X
X
Maintain Clock Suspend


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