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H55S1G62MFP-60 数据表(PDF) 5 Page - Hynix Semiconductor |
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H55S1G62MFP-60 数据表(HTML) 5 Page - Hynix Semiconductor |
5 / 53 page Rev 1.2 / Jul. 2008 5 11 1Gbit (64Mx16bit) Mobile SDR Memory H55S1G62MFP Series FEATURES ● Standard SDRAM Protocol ● Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) ● MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed ● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V ● LVCMOS compatible I/O Interface ● Low Voltage interface to reduce I/O power ● Programmable burst length: 1, 2, 4, 8 or full page ● Programmable Burst Type : sequential or interleaved ● Programmable CAS latency of 2 or 3 ● Programmable Drive Strength ● Low Power Features - Programmable PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Programmable DS (Drive Strength) - Deep Power Down Mode ● Operation Temperature - -30oC ~ 85oC ● Package - 54 Ball Lead Free FBGA 1Gb SDRAM ORDERING INFORMATION Part Number Clock Frequency CAS Latency Organization Interface Package H55S1G62MFP-60 166MHz 3 4banks x 16Mb x 16 LVCMOS 54 Ball FBGA H55S1G62MFP-75 133MHz 3 H55S1G62MFP-A3 105MHz 3 |
类似零件编号 - H55S1G62MFP-60 |
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类似说明 - H55S1G62MFP-60 |
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