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74ABT821DB 数据表(PDF) 8 Page - NXP Semiconductors |
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74ABT821DB 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74ABT821_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 February 2010 8 of 16 NXP Semiconductors 74ABT821 10-bit D-type flip-flop; positive-edge trigger; 3-state VM = 1.5 V. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. 3-state output (Qn) enable and disable times VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Set-up and hold times data input (Dn) to clock (CP) 001aal299 tPLZ tPHZ outputs disabled outputs enabled VOH − 0.3 V VOL + 0.3 V outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH 3.5 V VM GND GND tPZL tPZH VM VM 001aac738 VM CP input VM VM VM VM VM tsu(H) th(H) tsu(L) th(L) Dn input Vl GND Vl GND |
类似零件编号 - 74ABT821DB |
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类似说明 - 74ABT821DB |
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