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LTC2392-16 数据表(PDF) 16 Page - Linear Technology |
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LTC2392-16 数据表(HTML) 16 Page - Linear Technology |
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16 / 24 page  LTC2392-16 239216f applications inFormation Parallel Modes The parallel output data interface is active when the SER/PAR pin is tied low and when both CS and RD are low. The output data can be read as a 16-bit word as shown in Figures 8, 9 and 10 or it can be read as two 8-bit bytes by using the BYTESWAP pin. As shown in Figure 11, with the BYTESWAP pin low, the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to DO pins. When BYTESWAP is taken high, the eight LSBs now are output on the D15 to D8 pins and the eight MSBs are output on the D7 to D0 pins. Serial Modes The serial output data interface is active when the SER/PAR pin is tied high and when both CS and RD are low. The serial output data will be clocked out on the SDOUT pin when an external clock is applied to the SCLK pin. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 25MHz, a 500ksps throughput is achieved. The serial output data changes state on the rising edge of SCLK and can be captured on the falling edge of SCLK. D15 remains valid till the first rising edge of shift clock after the first falling edge of shift clock. The non-active digital outputs are high impedance when operating in the serial mode. The SDIN input pin is used to daisy-chain multiple con- verters. This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. For example, if two devices are cascaded, the MSB of the first device will appear at the output after 17 SCLK cycles. The first MSB is clocked in on the falling edge of the first SCLK. See Figure 12. Data Format When OB/2C is high, the digital output is offset binary. When low, the MSB is inverted resulting in two’s comple- ment output. This pin is active in both the parallel and serial modes of operation. Reset When the RESET pin is high, the LTC2392-16 is reset, and if this occurs during a conversion, the conversion is halted and the data bus is put into Hi-Z mode. In reset, requests for new conversions are ignored. Once RESET returns low, the LTC2392-16 is ready to start a new conversion after the acquisition time has been met. See Figure 13. Figure 8. Read the Parallel Data Continuously. The Data Bus is Always Driven and Can’t Be Shared CS = RD = 0 t4 t6 t16 tCONV CNVST BUSY DATA BUS D[15:0] PREVIOUS CONVERSION NEW 239216 F08 |
类似零件编号 - LTC2392-16 |
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类似说明 - LTC2392-16 |
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