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DM9000EP 数据表(PDF) 11 Page - Davicom Semiconductor, Inc.

部件名 DM9000EP
功能描述  ISA to Ethernet MAC Controller with Integrated 10/100 PHY
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制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.

DM9000EP 数据表(HTML) 11 Page - Davicom Semiconductor, Inc.

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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
11
Version: DM9000-DS-F03
April 23, 2009
6. Vendor Control and Status Register Set
The DM9000 implements several control and status
registers, which can be accessed by the host. These CSRs
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Register
Description
Offset
Default value
after reset
NCR
Network Control Register
00H
00H
NSR
Network Status Register
01H
00H
TCR
TX Control Register
02H
00H
TSR I
TX Status Register I
03H
00H
TSR II
TX Status Register II
04H
00H
RCR
RX Control Register
05H
00H
RSR
RX Status Register
06H
00H
ROCR
Receive Overflow Counter Register
07H
00H
BPTR
Back Pressure Threshold Register
08H
37H
FCTR
Flow Control Threshold Register
09H
38H
FCR
RX Flow Control Register
0AH
00H
EPCR
EEPROM & PHY Control Register
0BH
00H
EPAR
EEPROM & PHY Address Register
0CH
40H
EPDRL
EEPROM & PHY Low Byte Data Register
0DH
XXH
EPDRH
EEPROM & PHY High Byte Data Register
0EH
XXH
WCR
Wake Up Control Register
0FH
00H
PAR
Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Register
16H-1DH
XXH
GPCR
General Purpose Control Register
1EH
01H
GPR
General Purpose Register
1FH
XXH
TRPAL
TX SRAM Read Pointer Address Low Byte
22H
00H
TRPAH
TX SRAM Read Pointer Address High Byte
23H
00H
RWPAL
RX SRAM Write Pointer Address Low Byte
24H
04H
RWPAH
RX SRAM Write Pointer Address High Byte
25H
0CH
VID
Vendor ID
28H-29H
0A46H
PID
Product ID
2AH-2BH
9000H
CHIPR
CHIP Revision
2CH
00H
SMCR
Special Mode Control Register
2FH
00H
MRCMDX
Memory Data Read Command Without Address Increment
Register
F0H
XXH
MRCMD
Memory Data Read Command With Address Increment
Register
F2H
XXH
MRRL
Memory Data Read_ address Register Low Byte
F4H
00H
MRRH
Memory Data Read_ address Register High Byte
F5H
00H
MWCMDX
Memory Data Write Command Without Address Increment
Register
F6H
XXH
MWCMD
Memory Data Write Command With Address Increment
Register
F8H
XXH
MWRL
Memory Data Write_ address Register Low Byte
FAH
00H


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