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SE97PW 数据表(PDF) 14 Page - NXP Semiconductors |
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SE97PW 数据表(HTML) 14 Page - NXP Semiconductors |
14 / 55 page SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 14 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 7.9 SMBus/I2C-bus interface The data registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to ‘00h’, the location for the Capability register. The Pointer register latches the last location to which it was set. Each data register falls into one of three types of user accessibility: • Read only • Write only • Write/Read same address A ‘write’ to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways: • If the location latched in the Pointer register is correct (most of the time it is expected that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. • If the Pointer register needs to be set, then an address byte, pointer byte, repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to timing diagrams Figure 10 to Figure 13 for how to program the device. Fig 9. How SE97 responds to SMBus ALERT Response Address 0 0 0 1 1 A2 Alert Response Address 1 1 0 0 S 0 0 0 START bit read acknowledge 002aac685 A1 A0 0 1 P device address no acknowledge STOP bit host NACK and sends a STOP bit Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'. master sends a START bit, ARA and a read command host detects SMBus ALERT 1 A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 10. SMBus/I2C-bus write to the Pointer register 123456789123456789 SCL A6 A5 A4 A3 A2 A1 A0 SDA D7 D6 D5 D4 D3 D2 D1 D0 device address and write register address WA S START ACK by device P STOP A ACK by device 002aab308 |
类似零件编号 - SE97PW |
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类似说明 - SE97PW |
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