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ST7033 数据表(PDF) 7 Page - Sitronix Technology Co., Ltd. |
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ST7033 数据表(HTML) 7 Page - Sitronix Technology Co., Ltd. |
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7 / 39 page  ST7033 Ver 1.1 7/39 2009/07/17 6. PINNING DESCRIPTIONS Pin Name I/O Description Pin Count LCD driver outputs SEG0 to SEG95 O LCD segment driver outputs. The display data and the M signal control the output voltage of segment driver. Segment drover output voltage Display data Frame Normal display Reverse display H - VG VSS H + VSS VG L - VSS VG L + VG VSS Power save mode VSS VSS 96 COM0 to COM3 O LCD column driver outputs. The internal scanning data and the M signal control the output voltage of common driver. Common drover output voltage Display data Frame Normal display Reverse display H - XV0 H + V0 L - VM L + VM Power save mode VSS 68 MICROPROCESSOR INTERFACE PS[1,0] I Microprocessor interface mode selection pins. PS1 PS0 Interface Mode 1 1 8080-series parallel MPU interface 1 0 6800-series parallel MPU interface 0 1 4-line SPI MPU interface 0 0 3-line SPI MPU interface 2 /CSB I Chip select input pin. Data/instruction I/O is enabled only when /CSB is "L". When chip select is non-active, D7…D0 are high impedance. 1 /RESB I Reset input pin. When /RESB is "L", initialization is executed. 1 A0 I It determines whether the data bits are data or a command. A0=" H “: Indicates that D0 to D7 are display data. A0=" L “: Indicates that D0 to D7 are control data. There is no A0 pin in three line , so this pin can fix to ” H” 1 RW_WR I Read/Write operation control pin (if using Parallel interface). MPU Type RW_WR Interface Mode 6800-series R/W R/W=”H”: Read; R/W=”L”: Write. 8080-series /WR Signals (Instruction or Data) on data bus will be latched at the raising edge of this signal. 1 |
类似零件编号 - ST7033 |
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类似说明 - ST7033 |
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