Design Recommendations

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

9

5.2.1

Supply Voltage Sequencing and Separation Cautions

Figure 2. Supply Voltage Sequencing and Separation Cautions

5.2.1.1

Power Up Sequence

power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the

power supplies should be slower than 1

μs to avoid turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 ms or slower rise time for all supplies.

voltage regulator.

5.2.1.2

Power Down Sequence

Supplies Stable

2

1

3.3V

2.5V

1.5V

0

Time

Notes:

VDD should not exceed OVDD or VDDPLL by more than 0.4 V

at any time, including power-up.

Recommended that VDD should track OVDD/VDDPLL up to

0.9 V, then separate for completion of ramps.

Input voltage must not be greater than the supply voltage (OVDD,

VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up.

Use 1 ms or slower rise time for all supplies.

1.

2.

3.

4.