AD5541A/AD5542A/AD5512A

Preliminary Technical Data

Rev. P

rA | Page 8 of 24

Figure 10. AD5542A-1 10-Lead LFCSP Pin Configuration

14

IN V

13

DG ND

12

LDAC

11

DIN

10

NC

9

SCL K

8

NC = N O C O NN E CT

AD5542A

TO P V IE W

(No t to S cale)

Figure 11. AD5542 14-Lead SOIC Pin Configuration

NC = NO CO NNECT

1

2

3

4

5

6

7

8

VOUT

AGNDF

AGNDS

NC

REFF

REFS

RFB

CS

16

15

14

13

12

11

10

9

VLOGIC

INV

DGND

DIN

SCLK

CLR

LDAC

VDD

A D 5542A

TO P V IE W

(N o t to S cale)

Figure 12. AD5542A 16-Lead TSSOP Pin Configuration

12

11

10

1

3

4

DGND

LDAC

CLR

9

DIN

VOUT

AGNDS

2

AGNDF

REFS

TO P

VIEW

AD5542A

AD5512A

NC = NO CO NNECT

(No t to S cale)

Figure 13. AD5542A 16-Lead LFCSP Pin Configuration

Table 5. AD5542A/AD5512A Pin Function Descriptions

Pin No.

10-Lead

LFCSP

14-Lead

SOIC

16-Lead

TSSOP

16-Lead

LFCSP

Mnemonic

Description

8

1

1

16

RFB

Feedback Resistor Pin. In bipolar mode, connect this pin to the external op

amp output.

6

2

2

1

VOUT

Analog Output Voltage from the DAC.

3

3

2

AGNDF

Ground Reference Point for Analog Circuitry (Force).

4

4

3

AGNDS

Ground Reference Point for Analog Circuitry (Sense).

5

5

4

REFS

Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V

6

6

5

REFF

Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V

2

7

8

6

CS

Logic Input Signal. The chip select signal is used to frame the serial data

input.

3

8

9

8

SCLK

Clock Input. Data is clocked into the input register on the rising edge of SCLK.

Duty cycle must be between 40% and 60%.

5

11

10

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR

is low, all LDAC pulses are ignored. When CLR is activated, the input register

and the DAC register are cleared to the model selectable midscale or

zeroscale .

4

10

10

9

DIN

Serial Data Input. This device accepts 16-bit words. Data is clocked into the

input register on the rising edge of SCLK.

11

12

11

LDAC

LDAC Input. When this input is taken low, the DAC register is simultaneously

updated with the contents of the input register.

12

13

12

DGND

Digital Ground. Ground reference for digital circuitry.

7

13

14

13

INV

Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin

to external op amps inverting input in bipolar mode.

9

14

16

15

VDD

Analog Supply Voltage, 5 V ± 10%.

15

14

VLOGIC

Logic Power Supply.