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74HC595DR2G 数据表(PDF) 5 Page - ON Semiconductor |
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74HC595DR2G 数据表(HTML) 5 Page - ON Semiconductor |
5 / 13 page 74HC595 http://onsemi.com 5 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Parameter VCC (V) Guaranteed Limit Unit – 55 to 25_C v 85_C v 125_C fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 7) 2.0 3.0 4.5 6.0 6.0 15 30 35 4.8 10 24 28 4.0 8.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Shift Clock to SQH (Figures 1 and 7) 2.0 3.0 4.5 6.0 140 100 28 24 175 125 35 30 210 150 42 36 ns tPHL Maximum Propagation Delay, Reset to SQH (Figures 2 and 7) 2.0 3.0 4.5 6.0 145 100 29 25 180 125 36 31 220 150 44 38 ns tPLH, tPHL Maximum Propagation Delay, Latch Clock to QA − QH (Figures 3 and 7) 2.0 3.0 4.5 6.0 140 100 28 24 175 125 35 30 210 150 42 36 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to QA − QH (Figures 4 and 8) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to QA − QH (Figures 4 and 8) 2.0 3.0 4.5 6.0 135 90 27 23 170 110 34 29 205 130 41 35 ns tTLH, tTHL Maximum Output Transition Time, QA − QH (Figures 3 and 7) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 31 18 15 ns tTLH, tTHL Maximum Output Transition Time, SQH (Figures 1 and 7) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Cin Maximum Input Capacitance − 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State), QA − QH − 15 15 15 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Package)* Typical @ 25°C, VCC = 5.0 V pF 300 * Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). |
类似零件编号 - 74HC595DR2G |
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类似说明 - 74HC595DR2G |
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