L9D345G72BG5 datasheet(83/155 Pages) LODEV

部件名	L9D345G72BG5

功能描述	4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)

Download	155 Pages

Scroll/Zoom	100%

制造商	LODEV [LOGIC Devices Incorporated]

网页	http://www.logicdevices.com

标志

83 / 155 page

LOGIC Devices Incorporated

www.logicdevices.com

Jul 06, 2009 LDS-L9D345G72BG5-A

83

4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)

ADVANCE INFORMATION

L9D345G72BG5

High Performance, Integrated Memory Module Product

Initialization

The following sequence is required for power up and initialization, as shown in Figure 41.

Apply power. RESET\ is recommended to be below 0.2 x VccQ during power ramp to ensure the outputs remain disabled (HIGH-Z) and

1.

ODT off (RTT is also HIGH-Z). All other inputs, including ODT may be undeﬁned.

During power up, either of the following conditions may exist and must be met:

Condition A:

•

Vcc and VccQ are driven from a single power source and are ramped with a maximum delta voltage between them of ∆V≤300mV.

•

Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than Vcc, VccQ, Vss and VssQ must be

less than or equal to VccQ and Vcc on one side and must be greater than or equal to VssQ and Vss on the other side.

Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within

•

tVccPR=200ms.

Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within

•

tVccPR=200ms.

V

• REFDQ tracks Vcc x 0.5, VREFCA tracks Vcc x 0.5.

V

• TT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be

greater than or equal to zero to avoid device latchup.

• Condition B:

Vcc may be applied before or at the same time as VccQ.

•

VccQ may be applied before or at the same time as V

•

TT

, VREFDQ and VREFCA.

No slope reversals are allowed in the power supply ramp for this condition.

•

Until stable power, maintain RESET\ LOW to ensure the outputs remain disabled (HIGH-Z). After the power is stable, RESET\ must be

2.

LOW for at least 200μs to begin the initialization process. ODT will remain in the HIGH-Z state while RESET\ is LOW and until CKE is

registered HIGH.

CKE must be LOW 10ns prior to RESET\ transitioning HIGH.

3.

After RESET\ transitions HIGH, wait 500μs (minus one clock) with CKE LOW.

4.

After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be

5.

present and valid for at least 10ns (and a minimum of ﬁve clocks) and ODT must be driven LOW at least tIS prior to CKE being registered

HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete.

After CKE is registered HIGH and after

6.

tXPR has been satisﬁed, MRS commands may be issued. Issue an MRS (LOAD MODE) command

to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1).

Issue an MRS command to MR3 with the applicable settings.

7.

Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and conﬁguring ODT.

8.

Issue and MRS command to MR0 with the applicable settings, including a DLL RESET command.

9.

tDLLK (512) cycles of clock input are

required to lock the DLL.

Issue a ZQCL command to calibrate R

10.

TT

and RON values for the process voltage temperature (PVT). Prior to NORMAL operation. tZQINIT

must be satisﬁed.

When

11.

tDLLK and tZQINIT have been satisﬁed, the DDR3 SDRAM will be ready for normal operation.

OPERATIONS

类似零件编号 - L9D345G72BG5

制造商	部件名	数据表	功能描述
LOGIC Devices Incorpora...	L9D340G64BG2	3Mb / 155P	4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
	L9D340G64BG2E19	3Mb / 155P	4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
	L9D340G64BG2I15	3Mb / 155P	4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
	L9D340G64BG2M25	3Mb / 155P	4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)

More results

类似说明 - L9D345G72BG5

制造商	部件名	数据表	功能描述
LOGIC Devices Incorpora...	L9D340G64BG2	3Mb / 155P	4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
	L9D320G32BG6	3Mb / 154P	2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
	L9D364M64SBG2	3Mb / 159P	4.0 Gb, DDR3, 64 M x 64 Integrated Module
	L9D3256M72SBG2	3Mb / 160P	18-20 Gb, DDR3, 256 M x 72/80 Integrated Module
	L9D232M64SBG5	2Mb / 115P	2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module
Siemens Semiconductor G...	HYS6472V4200GU	76Kb / 15P	3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
	HYS64-72V2200GU-8	104Kb / 17P	3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
	HYS64-74V8200GU	84Kb / 17P	3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
	HYS64V1000GS-10	68Kb / 9P	3.3V 1M x 64-Bit SDRAM Module 3.3V 1M x 72-Bit SDRAM Module
	HYS64V8000GU	68Kb / 11P	3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module