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EBE51UD8AGWA-6E-E 数据表(PDF) 18 Page - Elpida Memory

部件名 EBE51UD8AGWA-6E-E
功能描述  512MB Unbuffered DDR2 SDRAM DIMM
Download  25 Pages
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51UD8AGWA-6E-E 数据表(HTML) 18 Page - Elpida Memory

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EBE51UD8AGWA
Preliminary Data Sheet E0921E10 (Ver. 1.0)
18
AC Characteristics (TC = 0
°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2 533]
(DDR2 SDRAM Component Specification)
-5C
Frequency (Mbps)
533
Parameter
Symbol
min.
max.
Unit
Notes
/CAS latency
CL
4
5
tCK
Active to read or write command delay
tRCD
15
ns
Precharge command period
tRP
15
ns
Active to active/auto refresh command time
tRC
60
ns
DQ output access time from CK, /CK
tAC
−500
+500
ps
DQS output access time from CK, /CK
tDQSCK
−450
+450
ps
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP
min.
(tCL, tCH)
ps
Clock cycle time
tCK
3750
8000
ps
DQ and DM input hold time
(differential strobe)
tDH (base)
225
ps
5
DQ and DM input hold time
(single-ended strobe)
tDH1 (base) –25
ps
DQ and DM input setup time
(differential strobe)
tDS (base)
100
ps
4
DQ and DM input setup time
(single-ended strobe)
tDS1 (base) –25
ps
Control and Address input pulse width for each input
tIPW
0.6
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
tCK
Data-out high-impedance time from CK,/CK
tHZ
tAC max.
ps
Data-out low-impedance time from CK,/CK
tLZ
tAC min.
tAC max.
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
300
ps
DQ hold skew factor
tQHS
400
ps
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
ps
DQS latching rising transitions to associated clock
edges
tDQSS
−0.25
+0.25
tCK
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS falling edge to CK setup time
tDSS
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
tCK
Mode register set command cycle time
tMRD
2
tCK
Write postamble
tWPST
0.4
0.6
tCK
Write preamble
tWPRE
0.35
tCK
Address and control input hold time
tIH (base)
375
ps
5
Address and control input setup time
tIS (base)
250
ps
4
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
tCK
Active to precharge command
tRAS
45
70000
ns
Active to auto-precharge delay
tRAP
tRCD min.
ns
Active bank A to active bank B command period
tRRD
7.5
ns


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