TC7MBL3257AFT/FK

2008-09-01

4

Characteristics

Symbol

Test Condition

Min

Max

Unit

3.3

± 0.3

⎯

0.31

Propagation delay time

(bus to bus)

Figure 1, Figure 2

(Note)

2.5

± 0.2

⎯

0.52

ns

3.3

± 0.3

⎯

11.0

Propagation delay time

(S to bus)

Figure 1, Figure 2

2.5

± 0.2

⎯

17.0

ns

3.3

± 0.3

⎯

11.0

Output enable time

(

Figure 1, Figure 3

2.5

± 0.2

⎯

17.0

ns

3.3

± 0.3

⎯

20.0

Output enable time

(S to bus)

Figure 1, Figure 3

2.5

± 0.2

⎯

22.0

ns

3.3

± 0.3

⎯

20.0

Output disable time

( OE to bus)

Figure 1, Figure 3

2.5

± 0.2

⎯

22.0

ns

3.3

± 0.3

⎯

20.0

Output disable time

(S to bus)

Figure 1, Figure 3

2.5

± 0.2

⎯

22.0

ns

Note: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay

other than the RC delay of the typical on resistance of the switch and the 50 pF load capacitance, when driven

by an ideal voltage the source (zero output impedance).

Capacitive Characteristics (Ta

= 25°C)

Characteristics

Symbol

Test Condition

Typ.

Unit

Control pin input capacitance ( OE , S)

(Note)

3.0

3

pF

Switch terminal capacitance (B1, B2)

OE

(Note)

3.0

15

pF

Switch terminal capacitance (A)

(Note)

3.0

26

pF

Note: This parameter is guaranteed by design.