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TC500ACOE713 数据表(PDF) 7 Page - Microchip Technology

部件名 TC500ACOE713
功能描述  Precision Analog Front Ends with Dual Slope ADC
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

TC500ACOE713 数据表(HTML) 7 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS21428E-page 7
TC500/A/510/514
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
TC500,
TC500A
TC510
TC514
Symbol
Function
CERDIP,
PDIP, SOIC
PDIP, SOIC
PDIP, SOIC
12
2
CINT
Integrator output. Integrator capacitor connection.
2
Not Used
Not Used
VSS
Negative power supply input (TC500/TC500A only).
33
3
CAZ
Auto-zero input. The auto-zero capacitor connection.
4
4
4
BUF
Buffer output. The Integrator capacitor connection.
5
5
5
ACOM
This pin is grounded in most applications. It is recommended that
ACOM and the input common pin (Ven- or CHn-) be within the analog
Common Mode Range (CMR).
66
6
CREF-
Input. Negative reference capacitor connection.
77
7
CREF+
Input. Positive reference capacitor connection.
88
8
VREF-
Input. External voltage reference (-) connection.
99
9
VREF+
Input. External voltage reference (+) connection.
10
15
Not Used
VIN-
Negative analog input.
11
16
Not Used
VIN+
Positive analog input.
12
18
22
A
Input. Converter phase control MSB. (See input B.)
13
17
21
B
Input. Converter phase control LSB. The states of A, B place the
TC5XX in one of four required phases. A conversion is complete
when all four phases have been executed:
Phase control input pins: AB =
00: Integrator zero
01: Auto-zero
10: Integrate
11: De-integrate
14
19
23
CMPTR OUT Zero crossing comparator output. CMPTR is high during the
integration phase when a positive input voltage is being integrated
and is low when a negative input voltage is being integrated. A high-
to-low transition on CMPTR signals the processor that the De-
integrate phase is completed. CMPTR is undefined during the auto-
zero phase. It should be monitored to time the integrator zero phase.
15
23
27
DGND
Input. Digital ground.
16
21
25
VDD
Input. Power supply positive connection.
22
26
CAP+
Input. Negative power supply converter capacitor (+) connection.
24
28
CAP-
Input. Negative power supply converter capacitor (-) connection.
—1
1
VOUT-
Output. Negative power supply converter output and reservoir
capacitor connection. This output can be used to power other
devices in the circuit requiring a negative bias voltage.
20
24
OSC
Oscillator control input. The negative power supply converter
normally runs at a frequency of 100 kHz. The converter oscillator
frequency can be slowed down (to reduce quiescent current) by
connecting an external capacitor between this pin and VDD (see
Section 2.0 “Typical Performance Curves”
).
18
CH1+
Positive analog input pin. MUX channel 1.
13
CH1-
Negative analog input pin. MUX channel 1.
17
CH2+
Positive analog input pin. MUX channel 2.
12
CH2-
Negative analog input pin. MUX channel 2.
16
CH3+
Positive analog input pin. MUX channel 3.
11
CH3-
Negative analog input pin. MUX channel 3.
15
CH4+
Positive analog input pin. MUX channel 4.
10
CH4-
Negative analog input pin. MUX channel 4
20
A0
Multiplexer input channel select input LSB (see A1).


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