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SA2159 数据表(PDF) 7 Page - Silan Microelectronics Joint-stock |
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SA2159 数据表(HTML) 7 Page - Silan Microelectronics Joint-stock |
7 / 11 page SA2159 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Rev: 1.0 2005.04.22 Http: www.silan.com.cn Page 7 of 11 Current programming An external Iset can set the size of the current source at the bottom of the core. Iset is normally determined by a resistor between V- and pin 5 (Vpin 5 = -2.7V, typically). Iset should be 200 µA larger than the total of the peak input and output signal currents because Iset divides into two portions: approximately 200 µA is used for internal biasing, and the rest is available for the current source at the bottom of the core. Note that since the sum of the input and output currents plus ISET must be supplied through the output impedance of the internal op amp, this impedance is approximately 2k Ω, the voltage available to drive the core will lower. Headroom The logarithmic characteristics of the core transistors also limit maximum signal currents. The devices used in the SA2159 are specially designed to conform to an ideal log-linear curve over a wide range of currents, but their limit value is approximately 1mA. Distortion will increase with increasing current levels because of falling log conformance. Figure 6 through 8 show typical distortion versus 1 kHz signal level for the SA2159 at -15dB, 0 dB, and +15dB gain. Thus, the maximum signal level for a particular design will be determined by the acceptable distortion. Figure 6. 1KHz THD +Noise Vs. input,-15dB gain Figure 7. 1kHz THD+Noise Vs. level, 0dB gain Figure 8. 1kHz THD+Noise Vs. Input, +15dB gain |
类似零件编号 - SA2159 |
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类似说明 - SA2159 |
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