2 / 15 page
STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A
Page 2 of 15
Pinouts
Pin Definitions
Pin Name
Alt
I/O Type
Description
A0–A12
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
DQ0-DQ7
Input/Output
Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
Figure 1. Pin Diagram - 28-Pin DIP
Figure 2. Pin Diagram - 28-Pin LLC
[+] Feedback