9

UC1875/6/7/8

UC2875/6/7/8

UC3875/6/7/8

In each of the output stages, transistors Q3 through Q6

form a high-speed totem-pole driver which will source

or sink more than one amp peak with a total delay of

approximately 30 nanoseconds. To ensure a low output

level prior to turn-on, transistors Q7 through Q9 form a

self-biased driver to hold Q6 on prior to the supply

reaching its turn-on threshold. This circuit is operable

when the chip supply is zero. Q6 is also turned on and

held low with a signal from the fault logic portion of the

chip.

APPLICATION INFORMATION (cont.)

Delay Blocks And Output Stages

The delay providing the dead-time is accomplished with

go high. The time is defined by the current sources, I1,

voltage on the Delay Set pins is internally regulated to

2.5V and the range of dead time control is

from 50 to 200 nanoseconds. NOTE: There is no way

to disable the delay circuitry, and the delay time must

be programmed.

The four outputs of the UC1875/6/7/8 interface to the full bridge converter switches as shown below:

Output Switch Orientation

UDG-95083

UDG-95082

3 Winding Bifilar, AWG 30 Kynar Insulation