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TPA3110D2PWPR 数据表(PDF) 2 Page - Texas Instruments |
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TPA3110D2PWPR 数据表(HTML) 2 Page - Texas Instruments |
2 / 33 page ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TPA3110D2 SLOS528 – JULY 2009....................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage AVCC, PVCC –0.3 V to 30 V SD, GAIN0, GAIN1, PBTL, FAULT –0.3 V to VCC + 0.3 V VI Interface pin voltage PLIMIT –0.3 V to GVDD + 0.3 V RINN, RINP, LINN, LINP –0.3 V to 6.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range(2) –40°C to 150°C Tstg Storage temperature range –65°C to 150°C BTL: PVCC > 15 V 4.8 RL Minimum Load Resistance BTL: PVCC ≤ 15 V 3.2 PBTL 3.2 Human body model (3) (all pins) ±2 kV ESD Electrostatic discharge Charged-device model (4) (all pins) ±500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The TPA3110D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad. (3) In accordance with JEDEC Standard 22, Test Method A114-B. (4) In accordance with JEDEC Standard 22, Test Method C101-A PACKAGE(1) TA ≤ 25°C DERATING FACTOR ( θ JA) TA = 85°C θ JP ΨJT 28 pin TSSOP (PWP) 4.48 W 27.87 °C/W 2.33 W 0.72 °C/W 0.45 °C/W (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Supply voltage PVCC, AVCC 8 26 V VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V VOL Low-level output voltage FAULT, RPULL-UP=100k, VCC=26V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2V, VCC = 18 V 50 µA IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA TA Operating free-air temperature –40 85 °C 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPA3110D2 |
类似零件编号 - TPA3110D2PWPR |
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类似说明 - TPA3110D2PWPR |
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