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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TSB12LV41A 数据表(PDF) 5 Page - Texas Instruments |
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TSB12LV41A 数据表(HTML) 5 Page - Texas Instruments |
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5 / 199 page  v 5 Detailed Operation and Programmers Reference 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 TSB12LV41A Configuration Register 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Version Register (VERS @ Addr 0h) 5–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 C Acknowledge Register (CACK @ Addr 4h) 5–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 B Acknowledge Register (BACK @ Addr 8h) 5–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Link Control Register (LCTRL @ Addr Ch) 5–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Interrupt Register/Interrupt Mask Register (IR @ Addr 10h/14h) 5–11 . . . . . . . . . . . . 5.7 Extended Interrupt Register/Extended Interrupt Mask Register (EIR @ Addr 18h/1Ch) 5–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Isochronous Receive Comparators Register 0 (IRPR0 @ Addr 20h) 5–16 . . . . . . . . 5.9 Isochronous Receive Comparators Register 1 (IRPR1 @ Addr 24h) 5–17 . . . . . . . . 5.10 Cycle Timer Register (CYCTIM @ Addr 28h) 5–18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Bus Time Register (BUSTIM @ Addr 2Ch) 5–18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Link Diagnostics Register (DIAG @ Addr 30h) 5–19 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Phy Access Register (PHYAR @ Addr 34h) 5–20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Expected Response (PHYSR @ Addr 38h) 5–21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Reserved Register (RESERVED @ Addr 3ch–40h) 5–21 . . . . . . . . . . . . . . . . . . . . . . . 5.16 Reserved Register (RESERVED @ Addr 3Ch) 5–21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 Reserved Register (RESERVED @ Addr 40h) 5–21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 Asynchronous Control Data Transmit FIFO Status (ACTFS @ Addr 44h) 5–22 . . . . 5.19 Bus Reset Data Register (BRD @ Addr 48h) 5–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 Bus Reset Error Register (BRERR @ Addr 4Ch) 5–23 . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 Asynchronous Control Data Receive FIFO Status (ACRXS @ Addr 50h) 5–24 . . . . 5.22 Reserved Register (RESERVED @ Addr 54h) 5–25 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23 Reserved Register (RESERVED @ Addr 55h – 7Fh) 5–25 . . . . . . . . . . . . . . . . . . . . . 5.24 Asynchronous Control Data Transmit FIFO First (ACTXF @ Addr 80h) 5–25 . . . . . . 5.25 Asynchronous Control Data Transmit FIFO Continue (ACTXC @ Addr 84h) 5–25 . 5.26 Asynchronous Control Data Transmit FIFO First & Update (ACTXFU @ Addr 88h) 5–25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.27 Asynchronous Control Data Transmit FIFO Last & Send (ACTXCU @ Addr 8ch) 5–25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.28 Reserved Register (RESERVED @ Addr 90h–BCh) 5–25 . . . . . . . . . . . . . . . . . . . . . . 5.29 Asynchronous Control Data Receive FIFO (ACRX @ Addr C0h) 5–26 . . . . . . . . . . . 5.30 Broadcast Write Receive FIFO (BWRX @ Addr 0C4h) 5–26 . . . . . . . . . . . . . . . . . . . . 5.31 Reserved Register (RESERVED @ Addr C8h) 5–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.32 Reserved Register (RESERVED @ Addr CCh) 5–26 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.33 Reserved Register (RESERVED @ Addr D0h) 5–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.34 Reserved Register (RESERVED @ Addr D4h) 5–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.35 Bulky Data Interface Control (BIF @ Addr D8h) 5–27 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.36 MPEG2 (DVB) Transmit Timestamp Offset Register (MXTO @ Addr DCh) 5–28 5.37 DSS Transmit Timestamp Offset Register (DXT0 @ Addr E0h) 5–28 . . . . . . . . . . . . . 5.38 MPEG2 (DVB)/DSS Receive Timestamp Offset (MRTO @ Addr E4h) 5–29 . . . . . . . 5.39 DSS Receive Timestamp Offset Register (DRT0 @ Addr E8h) 5–29 . . . . . . . . . . . . . 5.40 Asynchronous/Isochronous Application Data Control Register (AICR @ Addr ECh) 5–29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.41 MPEG2 (DVB)/DSS Formatter Control Register (MCR @ Addr F0h) 5–32 . . . . . . . . 5.42 DSS Formatter Control Register (DCR @ Addr F4h) 5–34 . . . . . . . . . . . . . . . . . . . . . . |
类似零件编号 - TSB12LV41A |
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类似说明 - TSB12LV41A |
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