TSB12LV21B

(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER

SLLS306– JULY 1998

6

POST OFFICE BOX 655303

Terminal Functions (Continued)

PCI address and data terminals

TERMINAL

I/O

FUNCTION

NAME

NO.

I/O

TYPE

FUNCTION

pci_ad31 – pci_ad29

pci_ad28

pci_ad27

pci_ad26

pci_ad25

pci_ad24

pci_ad23 – pci_ad21

pci_ad20

pci_ad19 – pci_ad16

pci_ad15 – pci_ad12

pci_ad11

pci_ad10

pci_ad9

pci_ad8

pci_ad7

pci_ad6 – pci_ad3

pci_ad2 – pci_ad0

169 – 171

173

174

176

3

4

9 – 11

13

15 – 18

36 – 39

41

43

44

47

50

52 – 55

57 – 59

I/O

Multiplexed PCI address and data signals. During the address phase of a primary bus PCI

cycle, pci_ad31:0 contain a 32-bit address or other destination information. During the data

phase pci_ad31:0 contain data

pci_cbe3

pci_cbe2

pci_cbe1

pci_cbe0

5

20

34

48

I/O

PCI Command/Byte enables

pci_par

32

I/O

PCI bus parity. In all PCI bus read and write cycles the PCILynx–2 calculates even parit-

across the pci_ad31:0 and pci_cbe3:0 signals. As an initiator during PCI cycles, the

PCILynx-2 outputs this parity indicator with a one pci_clk delay. As a target during PCI

cycles, the calculated parity is compared to the initiator’s parity indicator. A miscompare

can result in the assertion of a parity error (pci_perr).