TSB12C01A datasheet(11/59 Pages) TI

部件名	TSB12C01A

功能描述	High-Speed Serial-Bus Link-Layer Controller

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制造商	TI [Texas Instruments]

网页	http://www.ti.com

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11 / 59 page

1–5

Table 1–1. Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Phy Interface

CTL1, CTL0

62, 63

I/O

Control 1 and control 0 of the phy-link control bus. CTL1 and CTL0 indicate the four

operations that can occur in this interface (see Section 7 of this document or Annex

J of the IEEE 1394-1995 standard for more information about the four operations).

D0 – D7

52 – 55

57 – 60

I/O

Data 0 through data 7 of the phy-link data bus. Data is expected on D0 – D1 for

100 Mb/s packets, D0 – D3 for 200 Mb/s, and D0 – D7 for 400 Mb/s.

ISO

69

I

Isolation barrier (active low). This ISO is asserted (low) when an isolation barrier is

present.

LREQ

67

O

Link request. LREQ is a TSB12C01A output that makes bus requests and accesses

the phy layer.

POWERON

76

O

Power on indicator to phy interface. When active, POWERON has a clock output with

1/32 of the BCLK frequency and indicates to the phy interface that the TSB12C01A

is powered. This terminal can be connected to the link power status (LPS) terminal

on the TI phy devices to provide an indication of the LLC power condition.

SCLK

65

I

System clock. SCLK is a 49.152-MHz clock from the phy, that generates the

24.576-MHz clock.

Miscellaneous Signals

BCLK

32

I

Bus clock. BCLK is the host bus clock used in the host-interface module of the

TSB12C01A. It is asynchronous to SCLK.

CYCLEIN

42

I

Cycle in. CYCLEIN is an optional external 8,000-Hz clock used as the cycle clock,

and it should only be used when attached to the cycle-master node. It is enabled by

the cycle source bit and should be tied high when not used.

CYCLEOUT

44

O

Cycle out. CYCLEOUT is the TSB12C01A version of the cycle clock. It is based on

the timer controls and received cycle-start messages.

CYDNE

49

O

Status of CyDne bit. When the RevAEn bit of the control register is set, CYDNE

indicates the value of the CyDne bit of the interrupt register. When RevAEn is cleared,

CYDNE is a 3-state output.

CYST

50

O

Status of CySt bit. When the RevAEn bit of the control register is set, CYST indicates

the value of the CySt bit of the interrupt register. When RevAEn is cleared, CYST is

a 3-state output.

GND

1, 11,

21, 31,

38, 40,

41,

45–47,

51, 61,

66, 68,

70,

78–81,

91

Ground reference

GRFEMP

48

O

Status of Empty bit. When the RevAEn bit of the control register is set, GRFEMP

indicates the value of the Empty bit of the GRF status register. When RevAEn is

cleared, GRFEMP is a 3-state output.

RAMEz

77

I

RAM 3-state enable. When RAMEz is deasserted (low), FIFOs are enabled. When

RAMEz is asserted, the FIFOs are 3-state outputs. (This is a manufacturing

test-mode condition and should be grounded under normal operating conditions.)

类似零件编号 - TSB12C01A

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Texas Instruments	TSB12C01A	522Kb / 38P	[Old version datasheet] IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

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