 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TSB11LV01PT 数据表(PDF) 9 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
TSB11LV01PT 数据表(HTML) 9 Page - Texas Instruments |
|
|
9 / 21 page  TSB11LV01 3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 receiver PARAMETER TEST CONDITION MIN MAX UNIT IIC Common-mode input current Driver disabled –20 20 µA zID Differential input impedance Driver disabled 5 6 k Ω pF zIC Common-mode input impedance Driver disabled 20 24 k Ω pF VIT1 Receiver input threshold voltage –30 30 mV Cable-bias detect threshold, TPB cable input Driver disabled 0.6 1 V device PARAMETER TEST CONDITION MIN TYP MAX UNIT VIT2 Power status input threshold voltage (CPS) 400-k Ω resistor 4.7 7.5 V VOH High-level output voltage IOH = max, VCC = min VCC – 0.55 V VOL Low-level output voltage IOL = min, VCC = max 0.5 V Input current (LREQ, LPS, PD, PC0, PC1, PC2) VI=VCC or 0 ±1 µA IOZ High-impedance-state output current (CTL0, CTL1, D0, D1, C/LKON) VO= VCC or 0 ±5 µA P ll p inp t c rrent RESET VI =1.5 V –20 –40 –80 µA Pullup input current, RESET VI =0 –22 –45 –90 µA Power-up reset time, RESET 2 ms V(TO)+ Positive arbitration comparator threshold voltage 89 168 mV V(TO)– Negative arbitration comparator threshold voltage – 168 –89 mV VO TPBIAS output voltage 1.665 2.015 V ICC Supply current, receiver active VCC = 3.6 V 115 mA ICC(PD) Supply current, power-down mode VCC = 3 V 10 mA thermal characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT R θJA Junction-to-free-air thermal resistance Board mounted, No air flow 95 °C/W R θJA Junction-to-case-thermal resistance 19 °C/W switching characteristics PARAMETER MEASURED TEST CONDITION MIN MAX UNIT Jitter, transmit TPA, TPB ±0.8 ns Skew time, transmit Between TPA and TPB ±0.4 ns tr Rise time, transmit 10% to 90% RL = 55 Ω, CL = 10 pF 3.2 ns tf Fall time, transmit 90% to 10% RL = 55 Ω, CL = 10 pF 3.2 ns tsu Setup time, D, CTL, LREQ low or high before SYSCLK 50% to 50% See Figure 1 5 ns th Hold time, D, CTL, LREQ low or high after SYSCLK 50% to 50% See Figure 1 2 ns td Delay time, SYSCLK high to D, CTL low or high 50% to 50% See Figure 2 2 11 ns |
类似零件编号 - TSB11LV01PT |
|
类似说明 - TSB11LV01PT |
|
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
