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TLC2552ID 数据表(PDF) 8 Page - Texas Instruments |
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TLC2552ID 数据表(HTML) 8 Page - Texas Instruments |
8 / 23 page TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS276 –MARCH 2000 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, GND to VDD –0.3 V to 6.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog input voltage range –0.3 V to VDD + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference input voltage VDD + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital input voltage range –0.3 V to VDD+ 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating virtual junction temperature range, TJ –40 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA:C 0 °C to 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I –40 °C to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 2.7 3.3 5.5 V Positive external reference voltage input, VREFP (see Note 1) 2 VDD V Analog input voltage (see Note 1) 0 VDD V High level control input voltage, VIH 2.1 V Low-level control input voltage, VIL 0.6 V Setup time, CS falling edge (for 2551) or CS/FS falling edge (for 2552/55) before first SCLK falling edge, tsu(CSL-SCLKL) VDD = REF = 5.5 V 40 ns Hold time, CS rising edge after SCLK falling edge, th(SCLKL-CSH) 5 ns Delay time, delay from CS falling edge to FS rising edge (td(CSL-FSH) 0.5 7 SCLKs Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) 0.35 SCLKs Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL) 0.65 SCLKs Pulse width CS high time, twH(CS) 100 ns Pulse width FS high time, twH(FS) 0.75 SCLKs SCLK cycle time, VDD = 5.5–4.5 V, tc(SCLK) 50 10000 ns Pulse width low time, twL(SCLK) 0.4 0.6 SCLKs Pulse width high time, twH(SCLK) 0.4 0.6 SCLKs Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion time, tc) 0.1 µs Active CS/FS cycle time to reset internal MUX to AIN0, reset cycle TLC2552 only 4 7 SCLKs Operating free-air temperature TA TLC2551/2/5C 0 70 °C O erating free-air tem erature, TA TLC2551/2/5I –40 85 °C NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied to GND convert as all zeros(000000000000). 2. This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the sensor and A/D converter are placed several feet away from the controlling microprocessor. |
类似零件编号 - TLC2552ID |
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类似说明 - TLC2552ID |
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