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SN74SSTL16857 数据表(PDF) 1 Page - Texas Instruments

部件名 SN74SSTL16857
功能描述  14-BIT SSTL_2 REGISTERED BUFFER
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74SSTL16857 数据表(HTML) 1 Page - Texas Instruments

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SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
™ Family
D Supports SSTL_2 Signal Data Inputs and
Outputs
D Supports LVTTL Switching Levels on the
RESET Pin
D Differential CLK Signal
D Flow-Through Architecture Optimizes PCB
Layout
D Meets SSTL_2 Class II Specifications
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 14-bit registered buffer is designed for 2.3-V
to 3.6-V VCC operation and SSTL_2 data input
and output levels.
All inputs are compatible with the JEDEC
Standard for SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
When RESET is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs
are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS
RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
The SN74SSTL16857 is characterized for operation from 0
°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
RESET
CLK
CLK
D
Q
L
X
X
X
L
H
↓↑
HH
H
↓↑
LL
H
L or H
L or H
X
Q0
Copyright
© 1999, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VCC
D3
D4
D5
D6
D7
CLK
CLK
VCC
GND
VREF
RESET
D8
D9
D10
D11
D12
VCC
GND
D13
D14


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