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SN74GTLPH16612DGG 数据表(PDF) 1 Page - Texas Instruments |
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SN74GTLPH16612DGG 数据表(HTML) 1 Page - Texas Instruments |
1 / 11 page SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326 – MARCH 2000 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Members of the Texas Instruments (TI™) Widebus ™ Family D UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode D Translate Between GTLP Signal Levels and LVTTL Logic Levels D Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs D B-Port Transition Time Optimized for Distributed Backplane Loads D Ioff Supports Partial-Power-Down Mode Operation D Bus Hold on A-Port Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Distributed VCC and GND Pins Minimize High-Speed Switching Noise D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D Package Options Include Plastic Shrink Small-Outline (DL), and Thin Shrink Small-Outline (DGG) Packages NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR. description The SN74GTLPH16612 is a medium-drive, 18-bit UBT (universal bus transceiver) that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. This device provides a high-speed interface between cards operating at LVTTL logic levels and backplanes operating at GTLP signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing ( <1 V), reduced input threshold levels, and OEC ™ (output edge control). These improvements minimize bus settling time and have been designed and tested using several backplane models. Drvr VTT Conn. .25” .875” .625” .625” 1” 1” Slot 1 Slot 2 VTT .625” .625” 1” 1” Slot 16 Slot 8 .25” Conn. Conn. Conn. Rcvr Rcvr Rcvr t – Time – ns 10 30 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 020 TI GTLPH16612 Fairchild GTLP16612 TI GTL16612 Figure 1. Test Backplane Model With Output Waveform Results Copyright © 2000, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI, OEC, UBT, and Widebus are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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类似说明 - SN74GTLPH16612DGG |
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