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LTC2233UK 数据表(PDF) 20 Page - Linear Technology |
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LTC2233UK 数据表(HTML) 20 Page - Linear Technology |
20 / 28 page LTC2232/LTC2233 20 22323fa Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise perfor- mance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 1.5dB. See the Typical Performance Charac- teristics section. Driving the Encode Inputs The noise performance of the LTC2232/LTC2233 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC2232/LTC2233 is 105Msps (LTC2232) and 80Msps (LTC2233). For the ADC to operate properly, the encode signal should have a 50% ( ±5%) duty cycle. Each half cycle must have at least 4.5ns (LTC2232) or 5.9ns (LTC2233) for the ADC internal cir- cuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 20% to 80% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. APPLICATIO S I FOR ATIO Figure 11. Transformer Driven ENC+/ENC– VDD VDD LTC2232/LTC2233 22323 F11 VDD ENC– ENC+ 1.6V BIAS 1.6V BIAS 1:4 0.1 µF CLOCK INPUT 50 Ω 6k 6k TO INTERNAL ADC CIRCUITS |
类似零件编号 - LTC2233UK |
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类似说明 - LTC2233UK |
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