DW OR NT PACKAGE

(TOP VIEW)

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OEA

A1

A2

A3

A4

A5

A6

A7

A8

ERR

CLR

GND

B1

B2

B3

B4

B5

B6

B7

B8

PARITY

OEB

CLK

SN74ALS29833

8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995

Copyright

1

POST OFFICE BOX 655303

Generator/Checker

Outputs

Small-Outline (DW) Packages and Standard

Plastic (NT) 300-mil DIPs

description

The SN74ALS29833 is an 8-bit to 9-bit parity

transceiver designed for two-way communication

between data buses. When data is transmitted

from the A bus to the B bus, a parity bit is

generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error

(ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs

can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with an open-collector ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input.

The error-flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low,

data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error

condition that gives the designer more system diagnostic capability.

The SN74ALS29833 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT AND I/O

OEB

OEA

CLR

CLK

Ai

∑ of Hs

Bi†

∑ of Ls

A

B

PARITY

ERR‡

FUNCTION

L

H

X

X

Odd

NA

NA

A

L

NA

A data to B bus and generate parity

L

H

X

X

Even

NA

NA

A

H

NA

A data to B bus and generate parity

H

L

H

↑

NA

Odd

B

NA

NA

H

B data to A bus and check parity

H

L

H

↑

NA

Even

B

NA

NA

L

B data to A bus and check parity

X

X

L

X

X

X

X

NA

NA

H

Clear error-flag register

H

No

↑

X

NC

§

H

H

LNo

↑

X

X

Z

Z

Z

H

Isolation§

H

H

H

↑

Odd

X

Z

Z

Z

H

Isolation§

H

↑

Even

L

L

L

X

X

Odd

NA

NA

A

H

NA

A data to B bus and generate inverted

L

L

X

X

Even

NA

NA

A

L

NA

g

parity

NA = not applicable, NC = no change, X = don’t care

† Summation of high-level inputs includes PARITY along with Bi inputs.

‡ Output states shown assume ERR was previously high.

§ In this mode, ERR, when clocked, shows inverted parity of the A bus.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.