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SN74ABT3613PQ 数据表(PDF) 21 Page - Texas Instruments |
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SN74ABT3613PQ 数据表(HTML) 21 Page - Texas Instruments |
21 / 32 page SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS128F – JULY 1992 – REVISED APRIL 1998 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLKB FF B0–B35 SIZ1, SIZ0 ENB CSB W/RB EF CLKA CSA W/RA MBA ENA A0–A35 tsu(EN) th(EN) tc th(EN) tsu(EN) tpd(C-FF) FIFO Full tc tsk1† ta Previous Word in the FIFO Output Register Next Word From the FIFO tw(CLKH) tw(CLKL) To FIFO Low Low Low Low High th(EN) tsu(EN) th(D) tsu(D) High tw(CLKH) tw(CLKL) tpd(C-FF) 12 † tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, FF may transition high one CLKA cycle later than shown. NOTE A: Port-B size of long word is selected for the FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced from the rising CLKB edge that reads the first word or byte of the long word, respectively. Figure 10. FF-Flag Timing and First Available Write When the FIFO Is Full |
类似零件编号 - SN74ABT3613PQ |
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类似说明 - SN74ABT3613PQ |
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