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SN74ABT3613PQ 数据表(PDF) 20 Page - Texas Instruments |
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SN74ABT3613PQ 数据表(HTML) 20 Page - Texas Instruments |
20 / 32 page SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS128F – JULY 1992 – REVISED APRIL 1998 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(EN) tsu(EN) CLKA EF W1 A0–A35 MBA ENA CSA W/RA FF CLKB CSB W/RB SIZ1, SIZ0 ENB W1 B0–B35 tc tsu(EN) tw(CLKH) tw(CLKL) tpd(C-EF) FIFO Empty ta 12 Low High tw(CLKL) tw(CLKH) High th(EN) tsu(EN) th(D) tsu(D) tsk1† tc Low Low Low tpd(C-EF) th(EN) † tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EF high may occur one CLKB cycle later than shown. NOTE A: Port-B size of long word is selected for the FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EF is set low by the last word or byte read from the FIFO, respectively. Figure 9. EF-Flag Timing and First Data Read When the FIFO Is Empty |
类似零件编号 - SN74ABT3613PQ |
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类似说明 - SN74ABT3613PQ |
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