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SN74ABT3613PQ Datasheet(数据表) 7 Page - Texas Instruments

部件型号  SN74ABT3613PQ
说明  64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
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 7 page
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SN74ABT3613
64
× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128F – JULY 1992 – REVISED APRIL 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0–A35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
X
Active, mail2 register
None
L
L
H
L
Active, mail2 register
None
L
L
L
H
X
Active, mail2 register
None
L
L
H
H
Active, mail2 register
Mail2 read (set MBF2 high)
The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is read from the FIFO to the
B0–B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, EFB is high,
and either SIZ0 or SIZ1 is low (see Table 3).
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
SIZ1, SIZ0
CLKB
B0–B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
One, both low
In high-impedance state
None
L
H
H
Both high
In high-impedance state
Mail2 write
L
L
L
One, both low
X
Active, FIFO output register
None
L
L
H
One, both low
Active, FIFO output register
FIFO read
L
L
L
Both high
X
Active, mail1 register
None
L
L
H
Both high
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select
can change states during the setup- and hold-time window of the cycle.




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