SN54AHCT02, SN74AHCT02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303

CMOS) Process

JESD 17

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Small-Outline (D), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), Thin

Shrink Small-Outline (PW), and Ceramic

Flat (W) Packages, Ceramic Chip Carriers

(FK), and Standard Plastic (N) and Ceramic

(J) DIPs

description

These devices contain four independent 2-input

NOR gates that perform the Boolean function

Y = A

S B or Y = A + B in positive logic.

The SN54AHCT02 is characterized for operation

over the full military temperature range of –55

°C

to 125

°C. The SN74AHCT02 is characterized for

operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

X

L

X

HL

L

L

H

Copyright

© 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1Y

1A

1B

2Y

2A

2B

GND

4Y

4B

4A

3Y

3B

3A

SN54AHCT02 ...J OR W PACKAGE

SN74AHCT02 . . . D, DB, DGV, N, OR PW PACKAGE

(TOP VIEW)

32 1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4B

NC

4A

NC

3Y

1B

NC

2Y

NC

2A

SN54AHCT02 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.