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LPC1756 数据表(PDF) 33 Page - NXP Semiconductors |
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LPC1756 数据表(HTML) 33 Page - NXP Semiconductors |
33 / 71 page LPC1758_56_54_52_51_2 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 02 — 11 February 2009 33 of 71 NXP Semiconductors LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 7.29.8 Power domains The LPC1758/56/54/52/51 provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC1758/56/54/52/51, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC1758/56/54/52/51 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. |
类似零件编号 - LPC1756 |
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类似说明 - LPC1756 |
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