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SN74ABT8652 数据表(PDF) 10 Page - Texas Instruments |
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SN74ABT8652 数据表(HTML) 10 Page - Texas Instruments |
10 / 25 page SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 data register description boundary-scan register The boundary-scan register (BSR) is 38 bits long. It contains one boundary-scan cell (BSC) for each normal-function input and two BSCs for each normal-function I/O (one for input data and one for output data). The BSR is used to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output terminals, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input terminals. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, the value of each BSC is reset to logic 0 except BSC 36, which is reset to logic 1. The BSR order of scan is from TDI through bits 37–0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. Table 1. Boundary-Scan Register Configuration BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL 37 OEAB 31 A8-I 23 A8-O 15 B8-I 7 B8-O 36 OEBA 30 A7-I 22 A7-O 14 B7-I 6 B7-O 35 CLKAB 29 A6-I 21 A6-O 13 B6-I 5 B6-O 34 CLKBA 28 A5-I 20 A5-O 12 B5-I 4 B5-O 33 SAB 27 A4-I 19 A4-O 11 B4-I 3 B4-O 32 SBA 26 A3-I 18 A3-O 10 B3-I 2 B3-O –– –– 25 A2-I 17 A2-O 9 B2-I 1 B2-O –– –– 24 A1-I 16 A1-O 8 B1-I 0 B1-O boundary-control register The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE ™ instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 00000000010, which selects the PSA test operation with no input masking. The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associated test control signals. Table 2. Boundary-Control Register Configuration BCR BIT NUMBER TEST CONTROL SIGNAL BCR BIT NUMBER TEST CONTROL SIGNAL BCR BIT NUMBER TEST CONTROL SIGNAL 10 MASK8 6 MASK4 2 OPCODE2 9 MASK7 5 MASK3 1 OPCODE1 8 MASK6 4 MASK2 0 OPCODE0 7 MASK5 3 MASK1 |
类似零件编号 - SN74ABT8652 |
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类似说明 - SN74ABT8652 |
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