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EPM570M100A 数据表(PDF) 55 Page - Altera Corporation |
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EPM570M100A 数据表(HTML) 55 Page - Altera Corporation |
55 / 86 page Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices 4–5 Power-On Reset Circuitry © October 2008 Altera Corporation MAX II Device Handbook When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V is the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current path is from GND to the I/O pin, as shown in Figure 4–4. Power-On Reset Circuitry MAX II devices have POR circuits to monitor VCCINT and VCCIO voltage levels during power-up. The POR circuit monitors these voltages, triggering download from the non-volatile configuration flash memory (CFM) block to the SRAM logic, maintaining tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this process. When the MAX II device enters user mode, the POR circuit releases the I/O pins to user functionality. The POR circuit of the MAX II (except MAX IIZ) device continues to monitor the VCCINT voltage level to detect a brown-out condition. The POR circuit of the MAX IIZ device does not monitor the VCCINT voltage level after the device enters into user mode. More details are provided in the following sub-sections. Figure 4–4. ESD Protection During Negative Voltage Zap I/O I/O Gate Gate Drain Drain PMOS NMOS Source Source GND GND N+ N+ P-Substrate G S D |
类似零件编号 - EPM570M100A |
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类似说明 - EPM570M100A |
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