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EPM1270GF100A 数据表(PDF) 34 Page - Altera Corporation |
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EPM1270GF100A 数据表(HTML) 34 Page - Altera Corporation |
34 / 86 page 2–26 Chapter 2: MAX II Architecture I/O Structure MAX II Device Handbook © October 2008 Altera Corporation Figure 2–21 shows how a column I/O block connects to the logic array. I/O Standards and Banks MAX II device IOEs support the following I/O standards: ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ 3.3-V PCI Figure 2–21. Column I/O Block Connection to the Interconnect (Note 1) Note to Figure 2–21: (1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and one data_in input. Column I/O Block Contains Up To 4 IOEs I/O Block Local Interconnect R4 Interconnects LAB Local Interconnect C4 Interconnects LAB Local Interconnect C4 Interconnects 4 LAB LAB LAB data_out [3..0] 4 OE [3..0] 4 fast_out [3..0] Fast I/O Interconnect Path 4 data_in [3..0] Column I/O Block LAB Local Interconnect LAB Column Clock [3..0] |
类似零件编号 - EPM1270GF100A |
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类似说明 - EPM1270GF100A |
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