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EPM240T100A 数据表(PDF) 12 Page - Altera Corporation

部件名 EPM240T100A
功能描述  MAX II Device Family
Download  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM240T100A 数据表(HTML) 12 Page - Altera Corporation

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Chapter 2: MAX II Architecture
Logic Array Blocks
MAX II Device Handbook
© October 2008
Altera Corporation
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE
outputs in the same LAB. The local interconnect transfers signals between LEs in the
same LAB. LUT chain connections transfer the output of one LE’s LUT to the adjacent
LE for fast sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s register
within an LAB. The Quartus® II software places associated logic within an LAB or
adjacent LABs, allowing the use of local, LUT chain, and register chain connections
for performance and area efficiency. Figure 2–3 shows the MAX II LAB.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB local
interconnect is driven by column and row interconnects and LE outputs within the
same LAB. Neighboring LABs, from the left and right, can also drive an LAB’s local
interconnect through the DirectLink connection. The DirectLink connection feature
minimizes the use of row and column interconnects, providing higher performance
and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink
interconnects. Figure 2–4 shows the DirectLink connection.
Figure 2–3. MAX II LAB Structure
Note to Figure 2–3:
(1) Only from LABs adjacent to IOEs.
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Row Interconnect
Column Interconnect
Local Interconnect
LAB
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Fast I/O connection
to IOE (1)
Fast I/O connection
to IOE (1)
LE0
LE1
LE2
LE3
LE4
LE6
LE7
LE8
LE9
LE5
Logic Element


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