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EPM1270F100I 数据表(PDF) 72 Page - Altera Corporation |
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EPM1270F100I 数据表(HTML) 72 Page - Altera Corporation |
72 / 86 page 5–14 Chapter 5: DC and Switching Characteristics Timing Model and Specifications MAX II Device Handbook © Novermber 2008 Altera Corporation Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 2) Symbol Parameter –3 Speed Grade –4 Speed Grade –5 Speed Grade –6 Speed Grade –7 Speed Grade Unit Min Max Min Max Min Max Min Max Min Max t ACLK Address register clock period 100 — 100 — 100 — 100 — 100 — ns t ASU Address register shift signal setup to address register clock 20 — 20 — 20 — 20 — 20 — ns t AH Address register shift signal hold to address register clock 20 — 20 — 20 — 20 — 20 — ns t ADS Address register data in setup to address register clock 20 — 20 — 20 — 20 — 20 — ns t ADH Address register data in hold from address register clock 20 — 20 — 20 — 20 — 20 — ns t DCLK Data register clock period 100 — 100 — 100 — 100 — 100 — ns t DSS Data register shift signal setup to data register clock 60 — 60 — 60 — 60 — 60 — ns t DSH Data register shift signal hold from data register clock 20 — 20 — 20 — 20 — 20 — ns t DDS Data register data in setup to data register clock 20 — 20 — 20 — 20 — 20 — ns t DDH Data register data in hold from data register clock 20 — 20 — 20 — 20 — 20 — ns t DP Program signal to data clock hold time 0 —0— 0 — 0 — 0 — ns t PB Maximum delay between program rising edge to UFM busy signal rising edge — 960 — 960 — 960 — 960 — 960 ns t BP Minimum delay allowed from UFM busy signal going low to program signal going low 20 — 20 — 20 — 20 — 20 — ns t PPMX Maximum length of busy pulse during a program — 100 — 100 — 100 — 100 — 100 µs t AE Minimum erase signal to address clock hold time 0 —0— 0 — 0 — 0 — ns t EB Maximum delay between the erase rising edge to the UFM busy signal rising edge — 960 — 960 — 960 — 960 — 960 ns t BE Minimum delay allowed from the UFM busy signal going low to erase signal going low 20 — 20 — 20 — 20 — 20 — ns t EPMX Maximum length of busy pulse during an erase — 500 — 500 — 500 — 500 — 500 ms t DCO Delay from data register clock to data register output — 5 — 5 — 5 —5— 5 ns |
类似零件编号 - EPM1270F100I |
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类似说明 - EPM1270F100I |
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