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EPM570F100I 数据表(PDF) 73 Page - Altera Corporation |
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EPM570F100I 数据表(HTML) 73 Page - Altera Corporation |
73 / 86 page Chapter 5: DC and Switching Characteristics 5–15 Timing Model and Specifications © Novermber 2008 Altera Corporation MAX II Device Handbook t OE Delay from data register clock to data register output 180 — 180 — 180 — 180 — 180 — ns t RA Maximum read access time — 65 — 65 — 65 — 65 — 65 ns t OSCS Maximum delay between the OSC_ENA rising edge to the erase/program signal rising edge 250 — 250 — 250 — 250 — 250 — ns t OSCH Minimum delay allowed from the erase/program signal going low to OSC_ENA signal going low 250 — 250 — 250 — 250 — 250 — ns Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 2) Symbol Parameter –3 Speed Grade –4 Speed Grade –5 Speed Grade –6 Speed Grade –7 Speed Grade Unit Min Max Min Max Min Max Min Max Min Max |
类似零件编号 - EPM570F100I |
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类似说明 - EPM570F100I |
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