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EPM1270GF100I 数据表(PDF) 78 Page - Altera Corporation

部件名 EPM1270GF100I
功能描述  MAX II Device Family
Download  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM1270GF100I 数据表(HTML) 78 Page - Altera Corporation

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5–20
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
MAX II Device Handbook
© Novermber 2008
Altera Corporation
Table 5–26 shows the external I/O timing parameters for EPM2210 devices.
t
CNT
Minimum global clock
period for
16-bit counter
3.3
4.0
5.0
ns
f
CNT
Maximum global clock
frequency for 16-bit
counter
304.0 (1)
247.5
201.1
MHz
Note to Table 5–25:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
Table 5–25. EPM1270 Global Clock External I/O Timing Parameters (Part 2 of 2)
Symbol
Parameter
Condition
–3 Speed Grade
–4 Speed Grade
–5 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Table 5–26. EPM2210 Global Clock External I/O Timing Parameters
Symbol
Parameter
Condition
–3 Speed Grade
–4 Speed Grade
–5 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
PD1
Worst case pin-to-pin delay
through 1 look-up table
(LUT)
10 pF
7.0
9.1
11.2
ns
t
PD2
Best case pin-to-pin delay
through 1 LUT
10 pF
3.7
4.8
5.9
ns
t
SU
Global clock setup time
1.2
1.5
1.9
ns
t
H
Global clock hold time
0.0
0.0
0.0
ns
t
CO
Global clock to output delay
10 pF
2.0
4.6
2.0
6.0
2.0
7.4
ns
t
CH
Global clock high time
166
216
266
ps
t
CL
Global clock low time
166
216
266
ps
t
CNT
Minimum global clock
period for
16-bit counter
3.3
4.0
5.0
ns
f
CNT
Maximum global clock
frequency for 16-bit counter
304.0
(1)
247.5
201.1
MHz
Note to Table 5–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.


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